summaryrefslogtreecommitdiff
path: root/src
diff options
context:
space:
mode:
Diffstat (limited to 'src')
-rw-r--r--src/main.rs3
-rw-r--r--src/parser/mod.rs33
-rw-r--r--src/processor/mod.rs1
-rw-r--r--src/processor/registers.rs61
4 files changed, 98 insertions, 0 deletions
diff --git a/src/main.rs b/src/main.rs
index e7a11a9..a68851f 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -1,3 +1,6 @@
+pub mod parser;
+pub mod processor;
+
fn main() {
println!("Hello, world!");
}
diff --git a/src/parser/mod.rs b/src/parser/mod.rs
new file mode 100644
index 0000000..4cf7e00
--- /dev/null
+++ b/src/parser/mod.rs
@@ -0,0 +1,33 @@
+pub enum CommandType {
+ Label,
+ Mov,
+ Add,
+}
+
+pub enum CommandArgsType {
+ Nil,
+ Label,
+ NotLabel,
+}
+
+pub struct CommandArgs {
+ arg_type: CommandArgsType,
+ args_vec: Vec<String>,
+}
+
+pub struct Row {
+ pub command: CommandType,
+ pub args: CommandArgs,
+}
+
+#[test]
+fn check_row() {
+ let r: Row = Row {
+ command: CommandType::Mov,
+ args: CommandArgs {
+ arg_type: CommandArgsType::NotLabel,
+ args_vec: vec!["r0".to_string(), "r1".to_string()],
+ },
+ };
+ assert_eq!(r.args.args_vec[0], "r0");
+}
diff --git a/src/processor/mod.rs b/src/processor/mod.rs
new file mode 100644
index 0000000..8993d24
--- /dev/null
+++ b/src/processor/mod.rs
@@ -0,0 +1 @@
+pub mod registers;
diff --git a/src/processor/registers.rs b/src/processor/registers.rs
new file mode 100644
index 0000000..fbebd13
--- /dev/null
+++ b/src/processor/registers.rs
@@ -0,0 +1,61 @@
+pub struct CSPR {
+ n: bool,
+ z: bool,
+ c: bool,
+ v: bool,
+}
+
+impl CSPR {
+ pub fn new() -> Self {
+ CSPR {
+ n: false,
+ z: false,
+ c: false,
+ v: false,
+ }
+ }
+}
+
+pub struct Registers {
+ pub r1: i32,
+ r2: i32,
+ r3: i32,
+ r4: i32,
+ r5: i32,
+ r6: i32,
+ r7: i32,
+ r8: i32,
+ r9: i32,
+ r10: i32,
+ r11: i32,
+ r12: i32,
+ ip: i32,
+ sp: i32,
+ lr: i32,
+ pc: u32,
+ nzcv: CSPR,
+}
+
+impl Registers {
+ pub fn new() -> Self {
+ Registers {
+ r1: 0,
+ r2: 0,
+ r3: 0,
+ r4: 0,
+ r5: 0,
+ r6: 0,
+ r7: 0,
+ r8: 0,
+ r9: 0,
+ r10: 0,
+ r11: 0,
+ r12: 0,
+ ip: 0,
+ sp: 0,
+ lr: 0,
+ pc: 0,
+ nzcv: CSPR::new(),
+ }
+ }
+}