Use `name` instead of `rax` for showing the syscall name

3 files changed, 5 insertions, 5 deletions

diff --git a/src/registers.rs b/src/registers.rs
index 5832bc5..27ca8ea 100644
--- a/src/registers.rs
+++ b/src/registers.rs
@@ -41,7 +41,7 @@ impl RegistersData {
     }
 
     /// Return the rax name as syscall name
-    pub fn rax(&self) -> &str {
+    pub fn name(&self) -> &str {
         syscall_name(self.orig_rax)
     }
 
@@ -50,7 +50,7 @@ impl RegistersData {
         format!(
             "[{}]: {}({:x}, {:x}, {:x}, ...) = {:x}",
             self.date(),
-            self.rax().bold(),
+            self.name().bold(),
             self.rdi,
             self.rsi,
             self.rdx,
@@ -63,7 +63,7 @@ impl RegistersData {
         Line::from(vec![
             Span::raw(format!("[{}]: ", self.date())),
             Span::styled(
-                format!("{}", self.rax()),
+                format!("{}", self.name()),
                 Style::default().add_modifier(Modifier::BOLD),
             ),
             Span::raw(format!(
diff --git a/src/trace.rs b/src/trace.rs
index 2341394..157f2e7 100644
--- a/src/trace.rs
+++ b/src/trace.rs
@@ -66,7 +66,7 @@ pub fn trace(pid: Pid, args: &Args) -> anyhow::Result<Vec<RegistersData>> {
     while let Some(reg) = trace_next(pid)? {
         have_to_print ^= true;
         if have_to_print {
-            if !filters.is_empty() && !filters.contains(&reg.rax()) {
+            if !filters.is_empty() && !filters.contains(&reg.name()) {
                 continue;
             }
 
diff --git a/src/ui.rs b/src/ui.rs
index 1fe15e8..b7e342d 100644
--- a/src/ui.rs
+++ b/src/ui.rs
@@ -85,7 +85,7 @@ impl UI {
                 if let Some(reg) = trace_next(pid)? {
                     have_to_print ^= true;
                     if have_to_print {
-                        if !filters.is_empty() && !filters.contains(&reg.rax()) {
+                        if !filters.is_empty() && !filters.contains(&reg.name()) {
                             continue;
                         }
                         self.add_line(reg);